Senior Design Engineer 2
Xilinx
Hyderabad, Telangana, India
5d ago
source :

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative?

We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice.

From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable.

From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection.

We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Job Description

BS / MS EE, 6-10 yrs of relevant exp, 8+ years of design verification experience, inclusive of OOP coding experience (VERA, System Verilog, SpecmanE or C++) and SV Assertions, Strong Familiarity with Verification Methodologies such as UVM, Familiarity with Verilog and General Logic Design concepts, Knowledge of system-level architecture including buses like AXI / AHB, bridges, memory controllers such as DDR5 / DDR4 / LPDDR4 / LPDDR4, Strong working knowledge of UNIX environment and scripting languages such as Perl or Python, Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim, Experience using UNIX Revision Control tools - Subversion, RCS, CVS, Perforce and bug tracking tools such as Bugzilla, Experience in verifying multimillion gate chip designs from specifications to tape-out, Good knowledge on SVA with experience in property based formal verification.

Education Requirements

BS / MS EE, 6-10 yrs of relevant Years of Experience

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