The IPG (IP Engineering Group) is looking for energetic and passionate senior Verification (Pre-Silicon Validation) Engineers to verify high speed, state of the art complex digital IO controller designs (like PCIe, UPI, CXL etc).
Direct Responsibilities : Define & implement verification / validation tests / environment to verify high speed serial links IPs (PCIe, UPI, CXL etc).
Having extensive experience of defining and running system simulation models, and debugging RTL / tests etc is a must Should possess extensive knowledge of System Verilog / C++ / OVM or UVM methodology and / or Formal Verification candidate should have ability to work effectively with both internal and external teams / stakeholders, Strong problem solving / communication skills.
Should be a very strong team player.
Candidate should possess a Bachelor's degree with 12-14 years' experience or a Master's degree with 10-12 years' experience in VLSI, Electronics, Electrical, Computer Engineering or Computer Science (from reputed colleges like IIT / NIT, global universities).