Sr Principal Design Engineer
Cadence Design Systems, Inc.
BANGALORE
2d ago

1. Proficient in RTL coding, datapath designs, complex FIFO design 2. Strong knowledge of complete design flows and rigorous checks before delivery to other teams or customers ex- LINT, SDC, CDC, DFT, Low power, and trial PnR 3.

Good experience in microarchitecture, design, synthesis for a complex SerDes IP in various technology nodes. 4. Desired Protocols knowledge USB, PCIe, MIPI(DPHY), HDMI / Display 5.

Work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits 6.

Good understanding of working with signal processing IPs in terms of knowing calibrations, plls, dividers. Nature of work : The Candidate will be responsible for the design and implementation of high-speed SerDes PHY at the cutting edge nodes.

Responsibilities include the architecture of high-speed SerDes IP, design, lint, synthesis, static timing analysis, DFT, formal verification, at block, core, and chip levels.

Work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits Requirement : the Candidate is expected to have a good understanding of the design and implementation of a complex algorithm.

Proficient in high-speed design, RTL coding, datapath designs, complex FIFO design working at GHz frequencies. Good experience in microarchitecture, design, synthesis for a complex SerDes IP in various technology nodes.

Strong knowledge of complete design flows and rigorous checks before delivery to customers ex- LINT, SDC, CDC, DFT, Low power, and trial PnR

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