THE ROLE :
This is a Physical Design Engineering role that will require to take the design from RTL to GDS with Syntheis, Place n Route, Timing and Physical Verification
KEY RESPONSIBILITIES :
1. Must have specialized SoC implementation knowledge plus broader technical knowledge that facilitates more integrative thinking.
2. Have responsibility for projects or processes of significant technical importance and for results in SoC implementation and related areas.
3. Solve complex, novel and non-recurring problems; initiates significant changes to existing processes / methods and leads development and implementation.
4. Influences technical decisions that have a significant impact on final product.
5. Requires limited supervision and is evaluated according to project performance.
6. Coaches and mentors less experienced staff; influences others as a technical leader.
REQUIRED SKILLS :
1. SoC implementation expertise. Multi million gates integration.
2. Physical Synthesis, Constraints validation.
3. Floorplanning, Power planning.
4. Clock Tree Synthesis (CTS).
5. Scan Synthesis, Scan re-order.
6. Static Timing analysis (STA).
7. Analysis : IR, EM, Noise.
8. Physical Verification.
ACADEMIC CREDENTIALS :
Masters in VLSI / ECE / EE with relevant course work and project background with 7+ years of experience, or Bachelors with 9+ years of experience