Primary Responsibilities : The employee is responsible for the complete physical design of multiple large & complex ASIC and FPGA blocks, and will also contribute to fullchip design and integration for Achronix's FPGA products.
The employee is expected to take independent ownership of complex design challenges, which may include : - Floorplanning, Place & Route and CTS using physical design tools -
Physical verification - Physical Integration - Physical Design Methodology - STA - Bump planning, fullchip-level routing and tape-
out ready database creation The employee is expected to participate in methodology development activities, as well as participate in meetings across teams spanning Core technology, System engineering and Software engineering.
Skills : - Expertise in Physical Design activities : Floor-planning, CTS, P&R - Expertise in Physical Verification - Expertise with Physical Design & Verification tools -
A strong understanding of layout DRC rules & concepts and device identification concepts - Strong programming knowledge in Perl, TCL, and / or Shell Scripting -
Prior experience with bump planning and routing - Strong communication skills - Ability to work in a dynamic & fast-paced environment, with a pro-
active mindset - Experience in 16nm and smaller process nodes is a big plus - Experience in custom layout is a plus - Working knowledge of ICC2 & ICV is a plus Experience / Education : -
Preferred BS / MS 9 years of experience in physical design - Previous experience in 3-4 VLSI projects in deep submicron technologies (ref : hirist.com)