What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent : it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results.
It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.
If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
MTS Silicon Design Engineer IDC CPU Cores
THE ROLE :
As an experienced engineer in the RTL design team of the IDC Cores engineering group.
Your expertise in RTL design and coding will enable AMD to meet key goals such as power, performance, and area targets.
You will collaborate closely with a team of design engineers on a significant project in the early stages.
Execute on RTL design and coding for various sections of a given CPU features, microprocessor pipeline, and related logic to develop great technology
Collaborate with other teams assisting with design verification, synthesis, power reduction, timing convergence, and floor planning to realize a great design
PREFERRED SKILLS :
Ideally you bring the following experience and attributes to our team :
Experience in high-performance microprocessor design and microarchitecture
Verilog RTL development experience using industry tools in a CPU, SOC or ASIC environment such that you demonstrate strong facility with : Microprocessor architecture Logic design RTL coding experience for a high-speed processor Power saving techniques Strong problem solving and debugging skills Your commitment to innovating as a team as shown through excellent communication, knowledge of proper documentation techniques, and a track record of independently driving tasks to completion Breadth as well as depth as evidenced by exposure to physical design and verification methods and awareness of synthesis, place and route, and timing closure concepts
ADDITIONAL EXPERIENCE DESIRED :
Background in other aspects of ASIC implementation, especially with synthesis flow, static timing analysis (STA), and power flow (PTPX) will be a plus.
Knowledge of microprocessor design-for-test (DFT) and design-for-debug (DFD) logic will be a plus.
Experience in clocking, reset, power-up sequences and power management
Experience with x86 architecture, ARM or any other industry standard microprocessor ISA.
Scripting experience such as Perl, shell, and Tcl
Working knowledge of C / C++ / System Verilog / UVM with verif background will be a big plus.
ACADEMIC CREDENTIALS :
Master’s degree preferred with emphasis in Electrical / Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture