Qualcomm India Private Limited
Job Area :
Engineering Group, Engineering Group >
Job Overview :
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives.
But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products.
This is the Invention Age - and this is where you come in.
Verification Design Automation Mgr. will responsible for managing the BDC front-end CAD team. Collaborating with key stakeholders from Design & DV teams along with WW CAD leads.
Developing, implementing, and deploying automated methodologies and tool flows that are used to validate a multitude of wireless chips and IP cores / blocks.
As part of the Verification CAD, this position plays a critical role in driving next-generation verification methodologies through the deployment of semi and full-custom EDA tools that are used widely across the globe by the various ASIC digital design / verification teams.
As a Manager of the EDA CAD verification design automation team you will : Hire, Train and build the teams to develop and contribute technical aspects of many advanced verification methodologies and initiatives.
Key areas of focus involve Gate level Simulations, Low power simulation, Emulation, Simulation acceleration, and UVM methodology.
Work closely with cross-functional teams by leveraging domain-specific expertise and sharing / coordinating prototyping efforts, testing, and support.
Responsible for developing, implementing, and deploying advanced verification methodologies and flow automations across all chips and IP cores / blocks, as well as across simulation acceleration, Emulation, and post silicon validation.
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
Minimum Qualifications :
5 years of experience in ASIC / SoC Design Verification CAD including Core / IP or SoC verification
Experience in scripting for automation of design methodologies & flows
Experience using latest Verification methodologies such as System Verilog, and UVM
Working knowledge in one or more of the following : C, C++, Python, TCL or Perl.
Good to have hands-on experience in Verification regression automation Low Power using with UPF2.0. Emulation methodologies.
Multi-mode designs will be plus
Experience evaluating, designing, and deploying EDA tools in the area of Functional Verification, Simulation acceleration and Emulation.
Positive attitude and sound aptitude, willing to perform under challenging environment and ready to show ownership