Lead Physical Design Engineer - Python/C/ASIC (5-15 yrs) Bangalore (Semiconductor/VLSI/EDA)
Nuelearn Global Pvt Ltd
18h ago
source : iimjobs.com

Job Description :

  • Lead block / chip level PD activities for a lower technology node (16 nm and below).
  • PD activities include floor plans, abstract view generation, Top IR, RC extraction, PNR, STA, LEC, DRCs & LVS verification.
  • Process node experience to be in the range of 16nm & below (i.e.16 nm, 10 nm, 7 nm).
  • Work in advanced technology nodes as listed above at GHz speeds.
  • Working knowledge of Processor (CPU / GPU) is plus.
  • Working knowledge of DDR / PCIe is plus
  • We would love to hear from you if :

  • You have a degree in BE / BTECH / MTECH with 5+ years of experience in ASIC Physical Design.
  • You have a strong understanding of the RTL2GDSII flow or design implementation in leading process technologies
  • You have experienced in Cadence (EDI) or Synopsys (ICC) and Mentor (Calibre) EDA Tools.
  • You have good hands-on previous experience in scripting and / or flow development preferred in one or more of Perl, Tcl, Shell scripts, Python, C
  • ref : hirist.com)

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