SMTS Physical Design
Bangalore, India
5d ago

At Rambus, we are turning incredible possibilities into everyday reality by helping to deliver the innovations that greatly impact the world we live in.

We create leading-edge semiconductor and IP products, spanning memory and interfaces to security to smart sensors. Our products are integrated into tens of billions of devices and systems around the globe, running critical applications for Big Data, Internet of Things (IoT), mobile, consumer and media platforms.

And our history runs deep we have been in Silicon Valley for 25+ years and are continually anticipating key technology trends and are developing innovations that drive market changes.

From a pure IP provider to becoming a fabless chipmaker, Rambus is evolving to address critical challenges in the semiconductor industry.

As a dynamic organization, we are always seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to explore their passions to develop products that have real life impact.

As well, Rambus benefits are among the most comprehensive and competitive in Silicon Valley.

Physical Design Implementation of multi-million gate partitions / blocks, including Logic Synthesis, Floorplan, Place and Route, Clock Tree Synthesis, Timing closure, IR / EM and DRC / LVS closure for our highly challenging High-Speed designs in 7nm or similar advanced-node technologies.


  • Hands-on experience in Physical Design of High Performance / High Speed designs.
  • Experienced in hierarchical physical design with multiple voltage domains, multiple clock domains, multiple modes, and multiple corners.
  • Experience with implementation of high-speed interface such as DDR / PCIe / MIPI or high performance design such as ARM CPU sub-system or high performance bus architecture such as APB / AHB / AXI
  • Expertise with block level timing closure with good understanding of timing constraints, budgeting, EM / IR, block level STA, UPF / CPF flow and sign-off flows.
  • Strong P&R, Timing closure and Physical Verification skills with good knowledge of EDA tools from Cadence or Synopsys and Mentor Graphics required.
  • Preferred experience with Innovus, Genus, Voltus / Redhawk, Calibre, PrimeTime and StarRC.

  • Experience in 7nm or similar advanced technology nodes.
  • Experience with Low Power design methodologies is desirable.
  • Good scripting skills in TCL, PERL / Python.
  • Knowledge of Conformal LEC would be added advantage.
  • Self-driven individuals with good collaborative skills.
  • Open to mentoring junior team members.
  • Good verbal and written communication skills.
  • Qualifications

  • Bachelor’s or Master’s degree in Electrical / Electronics / Computer Science Engineering from reputed institution.
  • 6 10 years post-qualification experience in Physical Design
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