SoC FullChip Timing Lead
Intel
Bangalore, India
4d ago

Job Description

Lead PD / STA execution of partitions / subsystems / SoC with full ownership from synthesis to TI. Must have experience on 10nm and below technology nodes.

Responsible for schedule & quality goals. Responsible for stake holder management inside & outside D2S organization.

Drive & define FCT signoff criteria, setup, flow / methodology, constraints definition & validation, ACIO spec definition & validation & Syn & SD Caliber.

Drive TR to achieve best convergence methodology / flow, globals ( VISA / STF / TAP / DTF ) network definition & IP specific custom checks.

Drive TR to achieve best floorplan, package, PPA, TFM choice, signoff criteria & technology.

Expertise in all FCT Activities (Constraints definition & validation, TFM, efficient ECO methods etc ).

Qualifications

MTech in Microelectronics / VLSI is preferred with a minimum experience of 10yrs of experience in dealing with complex SoCs

Report this job
checkmark

Thank you for reporting this job!

Your feedback will help us improve the quality of our services.

Apply
My Email
By clicking on "Continue", I give neuvoo consent to process my data and to send me email alerts, as detailed in neuvoo's Privacy Policy . I may withdraw my consent or unsubscribe at any time.
Continue
Application form