Senior Design Engineer 1
Xilinx
Hyderabad, India, India
2d ago

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative?

At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice.

From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable.

From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection.

We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

The ideal candidate will have Masters with 2 to 5 years of circuit design experience in Analog IO and / or analog / digital PHY interfaces.

The candidate will be involved in leading edge design and implementation of IO / PHY designs in 16nm / 7nm and beyond. The position involves feasibility study of new architectures, implementing and verifying functionality of design meeting performance requirements of the product, working closely with CAD and other design teams in implementing designs using custom / structured-custom flows, some timing closure using PT flow etc..

Requirements for this position include :

1)Strong circuit design and device fundamentals in the areas of analog / IO / PHY & Mem Interface.

2)Hands on experience working with HSPICE / HSIM and well versed with all aspects of design functionality and performance verification.

3)Strong experience working with layout designers in understanding design / technology / layout constraints.

4)Analytical thinking ability and strong problem solving skills

5)Knowledge of physical design flows, timing closure expertise desired.

6)Sound expertise in scripting skills like Perl / Tcl

7)Excellent communication skills especially cross geographic interaction with overseas teams.

8)Good knowledge of SOC design methodology is desired.

9)Fast learner and an open mind to learn and contribute in any area / project.

Education Requirements M Tech or equivalent

Years of Experience 2 to 5 years

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