Assoc MTS,Logic Verification Engineering
13h ago


Roles & Responsibilities :

  • Develop test plans, tests and verification infrastructure for complex IP's / sub-system / SOC's
  • Create verification environment using UVM methodology
  • Create reusable bus functional models, monitors, checkers and scoreboards
  • Drive functional coverage driven verification closure
  • Work with architects, designers and post-silicon teams
  • Qualifications

    Skills / Qualifications :

  • Bachelor's / Masters degree in Electronics / Electrical Engineering
  • 0-1 year of verification experience
  • exposure in HVL based verification with expertise in SV & OVM
  • Exposure in High Speed IO verification (UFS / PCIE / XUSB)
  • Good understanding of memory technology and memory sub-system
  • Should have knowledge on all aspects of verification components & verification closure
  • Should have flair for documentation, defining / improving methodology and achieving productivity improvement
  • Ability to provide technical guidance & resolving technical conflicts desired
  • Ability to communicate technical and project issues to business and technical senior management
  • MUST have very good verbal and written communication skills
  • Apply
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