SOC Design Verification Staff
Qualcomm Technologies, Inc.
India - Bangalore
5d ago

Overview You will be responsible for SOC level verification of Debug (QDSS, DCC, JTAG, ScanDump) blocks. You will be contributing / leading the verification effort on cutting edge technology for complex Snapdragon series of SOCs You will be responsible for verification plan definition, DV environment development in SV / UVM, SV / C based test case development, Design verification at RTL level, DV Coverage analysis, Coverage improvement at block and SOC level, System scenario and use case verification, Power and Performance analysis for your blocks in SOC, Gate level verification, Functional test vector development and Silicon bring up debug support Minimum Qualifications 2-

10 years experience in Design verification in product company on real projects.

Knowledge about ARM Coresight Debug architecture.

Key words : Coresight, DFD, JTAG, Scandump, Crashreset, Trace Verification, Trigger Verification

Expertise in verifying complex designs from system as well as block level, through design flow.

Experience in building SV-UVM test environment / Assertion based verification.

Experience in coverage closure and test case improve to improve coverage

Experience in SYSTEM VERILOG, UVM, VERA , MODELSIM / VCS / SILOTI

Knowledge on Perl or any other scripting language

Understanding of RTL design / verification concept

Prior knowledge on security blocks, JTAG verification is an added advantage

Excellent written and oral communications skills.

Preferred Qualifications 2-10 years experience in Design verification in product company on real projects.Knowledge about ARM Coresight Debug architecture.

Key words : Coresight, DFD, JTAG, Scandump, Crashreset, Trace Verification, Trigger VerificationExpertise in verifying complex designs from system as well as block level, through design flow.

Experience in building SV-UVM test environment / Assertion based verification.Experience in coverage closure and test case improve to improve coverage Experience in SYSTEM VERILOG, UVM, VERA , MODELSIM / VCS / SILOTI Knowledge on Perl or any other scripting languageUnderstanding of RTL design / verification conceptPrior knowledge on security blocks, JTAG verification is an added advantageExcellent written and oral communications skills.

Education Requirements B Tech / M Tech

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