DSP Core Physical Design Sr Staff/Staff Engineer
Qualcomm Technologies, Inc.
Bangalore, India
5d ago

Job Overview

About QDSP Organization : QDSP organization is responsible for delivering high performance DSP cores that enable Qualcomm to deliver highly differentiated products across Mobile, Cloud, Voice & Music and Networking market segments.

The QDSP team in India, is responsible for end to end ownership across multiple DSP core deliverables per project across multiple segments.

The DSP cores play a key role in driving Connectivity (4G / 5G / LAN), Sensing, Audio, AI / ML workload and applications.

The responsibility includes : - The candidate is expected to be independent and capable of handling all aspects involving planning and execution of Netlist-to-GDSII on a DSP core.

The candidate should have a full exposure and hands on experience on all aspects of design flows like floorplanning, placement, CTS, routing, crosstalk avoidance, timing convergence, physical verification.

The candidate should be well versed with the core level timing closure (STA), timing closure methodologies, ECO generation and predictable convergence.

The candidate should be versed with parasitic extraction, LVS / DRC and other Physical verification checks; should be able to provide clear directions to the team wrt PNR issues.

The candidate will also be expected to drive methodology needs for DSP core with help of local and external CAD / EDA teams for faster design convergence.

Experience with high performance core such as CPU or GPU would be a bonus. Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.

8+ years Hardware Engineering experience or related work experience. Preferred Qualifications 10-15 year experience in Physical Design Execution.

Should have good exposure to high frequency design convergence and descent exposure to physical design methodologyMasters / Bachelors Degree in Electrical / Electronics science engineering with experience in IC design Experience in leading block level or chip level Timing closure & Physical Design activities.

Work independently in the areas of RTL to GDSII implementation Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.

Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.

Tcl / Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills

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