Qualcomm India Private Limited
Job Area :
Engineering Group, Engineering Group >
General Summary :
Experience in handling complex data path oriented Multi-million gate synthesis. Working Knowledge on Physical synthesis using tools like Genus, Fusion Compiler
Experience in developing constraints for multi-clock domains hierarchical / flat timing analysis
Good working knowledge in multi-power domain synthesis and structural power checks using CLP.
Hands-on experience in Formal verification along with strong debugging skills for resolving issues / aborts.
Good working knowledge in Pre-lyt STA and analyzing timing reports and generating timing ECOs
Good knowledge on analyzing trade-offs and recipes for timing / area / power / congestion.
Exposure in TCL scripting for usage in Synthesis / STA
Knowledge on Hierarchical STA with Hyperscale is a plus
Good team player. Need to interact with the stakeholders proactively
Ability to debug and solve issues independently
Minimum Qualifications :
Bachelor's degree in Engineering, Electronics or related field.