You will be part of a highly skilled high speed PHY design team working on challenging high speed PHY in latest foundry nodes (28nm, 14nm and below).
Most of the work will be in DDR3 / 4 and LPDDR3 / 4 designs.
You will undertake high speed analog / mixed signal designs of significant complexity and should be able to deliver high quality designs efficiently
For senior people, you will need to take ownership of complex analog sub-blocks inside the PHY and drive the specification, schedule and implementation including transistor and block level design, simulation, reliability, mixed mode simulations etc.
You may need to technically supervise junior engineers.
You will drive layout of complex blocks through mask designers. Conform to complex process rules as well as DFM.
You will participate in design reviews both internally and potentially with customers to explain design choices and robustness.
Work with people across multiple sites including overseas.
Help with creating IP views : Behavioral / Verilog-A, timing views, abstract etc.
Participate in silicon bring up, characterization, & perform Si correlations against models & simulations
4-12 Years’ experience in custom analog layout,
Bachelor’s or Master’s degree in Electrical Engineering,
Required Qualifications :
Circuit design experience in analog / mixed signal CMOS circuits in deep sub-micron technologies (65nm 10nm) in one or more of the following :
One or more High speed Serdes Interfaces (1Gbps-30Gbps. PCIe, MIPI, HDMI, USB, SATA, XFI, HMC, HDM, 10GKR etc.)
High speed Memory interfaces (DDR3 / 4, LPDDR3 / 4, GDDR)
Circuit design experience in one or more of the following sub-blocks in deep sub-micron technologies (65nm-10nm) :
PLL, DLL, Clock data recovery and low skew clock delivery
High speed receiver and transmitter front end and calibration methods
High speed I / O cell designs : LVDS, HSTL, SSTL, CML
For senior candidates (8+ yrs) :
proven track record of supervising complex and / or sensitive analog layout and defining floorplans
One or more production silicon and participation in bring-up and characterization
Experience is estimating circuit and layout complexity and coming up with resource and schedule requirements
Exposure to high speed PHY circuit concepts and sources of timing error
Desired qualifications :
Protocol level understanding of DDR timing and ability to evaluate circuit architecture to suit high speed DDR requirements is a big plus.
Experience with industry standard tools such as Cadence ADE, Spectre, AMS verification, EM / IR flows &, MATLAB, Calibre / StarRC etc..
Understanding of Mismatch analysis & MonteCarlo methodology / sims, transistor level & Circuit level noise analysis. Understanding of device physics & deep-sub micron issues