R&D Engineer, Sr II
Bangalore, INDIA
4d ago

Job Description

Synopsys HAPSĀ® Prototyping Solution improves time-to-market and helps avoid costly device re-spins by enabling early embedded software development and allowing hardware and software co-design well ahead of chip fabrication.

Synopsys delivers ProtoCompiler and HAPS solution, which dramatically accelerate software development, hardware verification and system validation from individual IP blocks to processor subsystems to complete SoCs.

We are looking for a Senior R&D engineer in ProtoCompiler R&D team for Partition flow in Bangalore for the following role and with the given background / skill sets.

Roles and responsibility :

A person in the position would be responsible for designing, developing, troubleshooting, debugging, and maintaining large and efficient software systems.

Work involves logic optimization, clock inference and marking, preparing design for partitioning, estimating area and reporting other design info and multi-processing the flow to get runtime improvement.

The person is expected to

Write requirement and functional specifications, design and implement efficient data structures and algorithms in C / C++.

Incorporate advanced software engineering tools and processes related to documentation and coding practices, memory and runtime profiling, coverage, unit testing in the development process.

Work with PV team in test planning, execution and with AE for customer support.

Maintain and support existing product and features.

Would be able to work in large and complex design automation environment.

Expected background and skill :

The person is expected to have :

B.Tech / M. Tech in CS / EE from a reputed institute.

8+ years of experience in designing, developing and maintaining large EDA software.

Solid background in digital design.

Expertise in data structures, graph algorithms and C / C++ programming on Unix / Windows.

Good familiarity with Verilog / VHDL RTL level designs, logic optimization and clock inferencing.

Working knowledge of FPGA prototyping, design tools and flows.

Experience with tools such as gprof, purify, coverity etc.


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