Mixed Signal IP Group IP's are in almost all Products of Intel, MIG IP require AE to resolve issues not limited to internal customers MIG partners within Intel but external customers of Intel.
AE should be able to influence IP R / D and Customers in all phases of Design Cycle , Architecture / Execution / Pre -Silicon Debug / Post Silicon Debug by ensuring no critical gaps / issue resolution at earliest.
Responsibilities : Ensure timely hands on debug and issue resolution in Pre Silicon / Post Silicon design issues. Hands on debug on IP / SoC environment.
Proactiveness in issue resolutions working with IP and Customers.Train juniors on protocol expertise and enhance debug skills and time for resolution.
Should develop IP expertise and be Point of Contact for customers outside MIG. Able to lead a team / program for entire design cycle right from IP3 / Architecture phase / Execution / Tape In / Post Silicon Support in terms of Debug / Resolution of issues which arise.
Able to work independently on IP and equipped to provide Onsite Technical Resolutions to customers either remotely or travel onsite.
Hands on experience in Logic Design / ValidationDebug expertise for Logic / Circuit Design IP in Pre Silicon and Post SiliconWork Experience 8+ yearsExperience in protocol PCIe / SATA / USB is a plusGood Debug skills in Pre Silicon Simulations / Post SI using Logic Analyzer Required to travel to onsite for customer product / IP development cycle
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms.
PEG strives to lead the industry moving forward through product innovation and world class engineering.
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