At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This job involves the development of DSP processors cores for Communications baseband processing. This involves :
Developing and testing customized instructions for accelerating baseband algorithms. using the TIE language.
Developing, debugging and optimizing examples and software libraries for Communications baseband algorithms
To make sure that the customized instructions are optimized considering hardware gate count & power and verification of the customized instructions.
Generating the engineering and customer documentation.
The candidate should have a good experience in developing and optimizing core signal processing algorithms ( for communication or muti-
media domain) in C and assembly-language / intrinsic programming for a DSP or DSP-like processor.
The candidate should have a good knowledge of processor ISA / architecture for at least 1-2 DSP and should have a strong grasp of the issues surrounding software performance tuning for the given DSP ISA / architecture.
The candidate should have experience in applying principles of good software and interface design, and should have experience with at least one revision control system.
Good technical communication skills are required.
Candidate must be self-motivated and capable of working independently or as part of a team.
Experience / knowledge of Wireless Communications PHY standards will be a plus.
3-5 years work experience in optimization of DSP algorithms / modules for a given DSP
Candidates with higher experience may also be considered.
Educational qualification : BE / BS in CS or EE is required, MTech / MS is preferred.
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