Digital Design Engineer
Intel Corporation
Bangalore, KA, IN
21d ago

Job Description

Job Requirement : In this position, you will be responsible for all aspects of STA & timing closure activities of Intel's SoCs in lower technology nodes.

Your tasks will include but not limited to : Design & Architecture understanding, Interaction with FE / DFT / Verification teams, Clocking, Constraints development, ACIO Timing, Understanding on synchronous & asynchronous paths, Clock domain crossing issues, Understanding and debugging extraction issues, Deciding timing signoff modes & corners, Design margins, Hierarchical timing including IO budgeting for partitions, Drive the designs to timing closure, interacting / supporting synthesis and APR team during timing closure cycle, timing ECOs, Timing model build, Timing signoff & quality checks.

You will also be part of debug / troubleshoots for a wide variety of tasks up to and including difficult / critical design issues and proactive intervention, as required.

Qualifications

Qualification : Education : B.Tech. or M.Tech. in Electrical / Electronics Engineering with 5 to 10 years' of experience.

Preference : Master's Degree in Electrical / Electronics Engineering with VLSI / microelectronics specialization, with 5 to 10 years of experience in STA.

Key Skills : - In-depth knowledge & hands-on experience with the overall silicon implementation flows and methodologies such a STA, Synthesis, Clocking is required.

Good understanding & exposure of overall Timing closure cycle in SoC. - Good scripting skills in TCL / Perl / Shell. Expertise in STA signoff tools PT / ETS.

  • Skill in Synopsys tools PT / DC & exposure to ICC will be an added advantage. - Solid understanding of process and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-
  • offs. - Solid technical and good communication skills.

    Inside this Business Group

    The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms.

    PEG strives to lead the industry moving forward through product innovation and world class engineering.

    Legal Disclaimer :

    Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

    It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews.

    We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money.

    We would urge people interested in working for Intel, to apply directly at and not fall prey to unscrupulous elements.

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