Job description :
â€¢Independent planning and execution of Netlist-to-GDSII.
â€¢Full exposure to all aspects of design flows like floor planning, placement, CTS, routing, crosstalk avoidance, physical verification.
â€¢Should have good exposure to high frequency design convergence and exposure to physical design methodology.
â€¢3+ years of experience in IC design Experience in leading block level or chip level Timing closure & Physical Design activities.
Work independently in the areas of RTL to GDSII implementation.
â€¢Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
â€¢Knowledge of low power flow (power gating, multi-VT flow, power supply management etc.).
â€¢Circuit level comprehension of time critical paths in the design. Tcl / Perl scripting.
â€¢Willing to handle technical deliveries with a small team of engineers.
â€¢Well versed with the level timing closure (STA), timing closure methodologies, ECO generation and predictable convergence.
â€¢Well versed with parasitic extraction, LVS / DRC and other Physical verification checks.
â€¢Should be able to provide clear directions to the team wrt PNR issues.
â€¢Drive methodology with help of local and external CAD / EDA teams for faster design convergence.
â€¢Well aware of place and route methodologies and hands on experience with timing convergence.
â€¢Qualification : Strong problem-solving skills and teamwork, Self-motivated, excellent verbal and written communication.
Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)