Principal ASIC Design Engr
Bangalore, India
9d ago

Your Key Responsibilities Would Include :

Job description :

Work with system-level architects and identify ASIC / FPGA / IP level requirements based on system level requirements. Document the requirements and partition the design at a high level.

Review design trade-offs and provide high-level guidance for ASICs / FPGA or IP. Job includes the study of applicable industry standards and evaluating their impact on internal designs and architecture.

Micro-architecture and design of ASIC / FPGA : Includes design documentation, review, RTL coding using Verilog, synthesis using industry standard tools including FPGA tools.

Take the design through complete flow consisting of lint / CDC checks, sdc constraints, synthesis and post netlist checks.

define APIs at chip / module level, design chip / FPGA level clocking, IOs and reset architecture. Job includes ASIC / FPGA level architecture, implementation, verification support and lab validation.

Requirements :

  • 10+ years of experience in ASIC Design.
  • Participation in at least 1 full ASIC cycle as a designer from Arch to Bringup · Good knowledge and experience in RTL / Synthesis based ASIC design methodology and tools
  • Proven experience in the architecture of complex ASICs / FPGAs .
  • Networking and packet based protocol experience is desired
  • Experience in SONET, OTN or Ethernet based technology is preferred
  • Must have good communication skills.
  • Must have ability and desire to work as a team
  • Education & Experience Necessary For Success :

    Candidates must have a Bachelor's Degree or higher in Electronics and Communication / VLSI / Microelectronics with very good academics.

    Master’s degree preferred.

    Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability.

    EEO Employer / Vet / Disabled.

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