Should have minimum 3 years of experience in ASIC / IP / Soc Verification.
Â· Minimum 2-3 years of experience in development of SV based testbench.
Â· Constrained Random Verification - System Verilog.
Â· Should have good command
Salary : Not Disclosed by Recruiter
Employment Type : Permanent Job, Full Time
System Verilog SOC Verification ASIC Verification Sv
Desired Candidate Profile
Please refer to the Job description above